1. Field of Invention
The present invention relates to non-volatile memory. More particularly, the present invention relates to non-volatile memory with horizontal memory cells and vertical memory cells.
2. Description of Related Art
Non-volatile memory has its wide applications in various field, such as the multimedia or particularly to the portable multi-media applications including digital camera and audio player, or the smart cellular phone. All of these apparatus need to store data or contents when power is off. Non-volatile memory then has various applications.
Basically, the Non-volatile memory device includes multiple memory cells arranged in an array manner. Usually, one memory cells can store a binary data. Conventionally, the memory cell, such as volatile memory of DRAM, is formed by a metal-oxide semiconductor (MOS) transistor with a capacitor, wherein the capacitor is used to store the data. However, for the non-volatile memory, such as PROM or EPROM, the memory cell structures include floating gate and control gate, wherein the floating gate is used to store the binary data. When the memory cell size has been greatly reduced, a memory cell with oxide-nitride-oxide (ONO) structure has also been proposed.
FIG. 1 is a cross-sectional drawing, schematically illustrating a conventional MOS memory cell with the ONO structure to have memory function. In FIG. 1, a semiconductor substrate 100, such as a P-type silicon substrate, is provided. A gate structure stack is formed on the substrate 100, and the doped regions 110, such as N+ doped region, are formed in the substrate at each side of the gate structure stack. The gate structure stack includes a tunnel oxide layer 108, a trapping layer 106 and a control oxide layer 104, which are sequentially formed on the substrate 100. Then, a gate layer, such as a polysilicon layer 102, serving as a control gate, formed on the control oxide layer 104. The photolithographic and etching processes are performed to pattern the stacked layer, so as to form the gate structure stack.
For this memory cell structure in FIG. 1, during a writing process for example, a proper voltage is applied on the control gate 102, then the electrons tunneling from the tunnel oxide layer 108 and are trapped in the trapping layer 106 to store a binary data. A control oxide 104 is located between the trapping layer 106 and a control gate electrode 102. Taking the N-type MOS memory cell as an example, the substrate 100 is a P-type well. The doped region 110 is the N+ region. Basically, the layers 104, 106, and 108 form a structure of oxide/nitride/oxide (ONO) layer with memory function. The mechanism of Fowler-Nordheim (FN) Tunneling effect is employed for programming the memory cell. By applying proper voltages on the gate electrode, source region, drain region, and the substrate, electrons can be injected into or driven out from the trapping layer 106, so as to achieve the programming and erasing function. In reading process, depending on the status of electrons stored in the trapping layer 106, the binary data can be read. In other words, the cell VT (threshold voltage) could be programmed to high VT by F-N mechanism, due to electrons being trapped in the thin dielectric layer, and cell can be erased to low VT by F-N mechanism, due to electrons being de-trapped from the thin dielectric layer. So the cell device can perform the storage function for non-volatile memory. The mechanism is known by the ordinary skilled artisans and is not described in better detail.
By using the memory cell in FIG. 1, a memory array device, such as a NOR type flash memory, is conventionally proposed as shown in FIG. 2. In FIG. 2, the memory array structure is composed by memory cells 200. Each cell 200 has it's own word line WL, bit line BL and source ground. It can be selected and deselected through the control on the word line and bit line.
Another conventional memory array device is shown in FIG. 3. In FIG. 3, The NAND flash memory design has more compact cell array structure, comparing with NOR type flash. The memory cells 300 are connected in series manner. The bit line BL and the source line are common in the same diffusion region. The bit line area and source area are shared with the previous cell and next cell. In this manner, the cell pitch is more compact, so that it is suitable for data storage with low cost per bit.
It still has several types of conventional flash memory, such as AND type, DINOR type. However, a novel type of flash memory with better compact or better operation algorithm is still desired by the manufactures.